1. Field of the Invention
The present invention relates to a stacked capacitor used in a memory cell of a dynamic random access memory (DRAM) device.
2. Description of the Related Art
Generally, in a DRAM device, each memory cell is constructed by a MOS transistor and a capacitor. A stacked capacitor, which has lower and upper electrodes and an insulating layer therebetween, has been used as such a capacitor. Since the stacked capacitor is three-dimensional, the capacitance thereof can be increased, to thereby enhance the integration of the DRAM device.
In a prior art stacked capacitor type DRAM device, an insulating layer is formed on a semiconductor substrate. A capacitor electrode layer is formed on the insulating layer and is electrically connected via a contact hole of the insulating layer to an impurity doped region of the semiconductor substrate. Also, a capacitor insulating layer is formed on the capacitor lower electrode layer, and a capacitor upper electrode layer is formed on the capacitor insulating layer. This will be explained later in detail.
In the above-described prior art stacked capacitor type DRAM device, however, a step between a memory cell array area and a peripheral circuit area is so large that it is difficult to arrange wiring patterns around an interface between the memory cell array area and the peripheral circuit area. Particularly, when the device is highly integrated, the depth of focus of an exposure system used in a lithography process is reduced, so that a fine pattern cannot be formed on such a step.